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M28F101
1 Mb (128K x 8, Chip Erase) FLASH MEMORY
5V 10% SUPPLY VOLTAGE 12V PROGRAMMING VOLTAGE FAST ACCESS TIME: 70ns BYTE PROGRAMING TIME: 10s typical ELECTRICAL CHIP ERASE in 1s RANGE LOW POWER CONSUMPTION - Stand-by Current: 100A max 10,000 ERASE/PROGRAM CYCLES INTEGRATED ERASE/PROGRAM-STOP TIMER OTP COMPATIBLE PACKAGES and PINOUTS ELECTRONIC SIGNATURE - Manufacturer Code: 20h - Device Code: 07h DESCRIPTION The M28F101 FLASH Memory is a non-volatile memory which may be erased electrically at the chip level and programmed byte-by-byte. It is organised as 128K bytes of 8 bits. It uses a command register architecture to select the operating modes and thus provides a simple microprocessor interface. The M28F101 FLASH Memory is suitable for applications where the memory has to be reprogrammed in the equipment. The access time of 70ns makes the device suitable for use in high speed microprocessor systems.
32
1
PDIP32 (P)
PLCC32 (K)
TSOP32 (N) 8 x 20 mm
Figure 1. Logic Diagram
VCC
VPP
17 A0-A16
8 DQ0-DQ7
Table 1. Signal Names
A0-A16 DQ0-DQ7 E G W VPP VCC VSS April 1997 Address Inputs Data Inputs / Outputs Chip Enable Output Enable Write Enable Program Supply Supply Voltage Ground
W E G
M28F101
VSS
AI00666B
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M28F101
Figure 2A. DIP Pin Connections Figure 2B. LCC Pin Connections
VPP A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS
1 32 2 31 3 30 4 29 5 28 6 27 7 26 8 25 M28F101 9 24 10 23 11 22 12 21 13 20 14 19 15 18 16 17
AI00667
VCC W NC A14 A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
A7 A6 A5 A4 A3 A2 A1 A0 DQ0
A12 A15 A16 VPP VCC W NC 1 32 A14 A13 A8 A9 A11 G A10 E DQ7 9 M28F101 25 17 DQ1 DQ2 VSS DQ3 DQ4 DQ5 DQ6
AI00668
Warning: NC = Not Connected.
Warning: NC = Not Connected.
Figure 2C. TSOP Pin Connections
Figure 2D. TSOP Reverse Pin Connections
A11 A9 A8 A13 A14 NC W VCC VPP A16 A15 A12 A7 A6 A5 A4
1
32
8 9
M28F101 (Normal)
25 24
16
17
AI00669B
G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2 A3
1
32
8 9
M28F101 (Reverse)
25 24
16
17
AI00670C
A11 A9 A8 A13 A14 NC W VCC VPP A16 A15 A12 A7 A6 A5 A4
Warning: NC = Not Connected.
Warning: NC = Not Connected.
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M28F101
Table 2. Absolute Maximum Ratings
Symbol TA TSTG VIO VCC VA9 VPP Parameter Ambient Operating Temperature Storage Temperature Input or Output Voltages Supply Voltage A9 Voltage Program Supply Voltage, during Erase or Programming Value -40 to 125 -65 to 150 -0.6 to 7 -0.6 to 7 -0.6 to 13.5 -0.6 to 14 Unit C C V V V V
Note: Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other relevant quality documents.
DEVICE OPERATION The M28F101 FLASH Memory employs a technology similar to a 1 Megabit EPROM but adds to the device functionality by providing electrical erasure and programming. These functions are managed by a command register. The functions that are addressed via the command register depend on the voltage applied to the VPP, program voltage, input. When VPP is less than or equal to 6.5V, the command register is disabled and M28F101 functions as a read only memory providing operating modes similar to an EPROM (Read, Output Disable, Electronic Signature Read and Standby). When VPP is raised to 12V the command regsiter is enabled and this provides, in addition, Erase and Program operations. READ ONLY MODES, VPP 6.5V For all Read Only Modes, except Standby Mode, the Write Enable input W should be High. In the Standby Mode this input is don't care. Read Mode. The M28F101 has two enable inputs, E and G, both of which must be Low in order to output data from the memory. The Chip Enable (E) is the power control and should be used for device selection. Output Enable (G) is the output control and should be used to gate data on to the output, independant of the device selection. Standby Mode. In the Standby Mode the maximum supply current is reduced. The device is placed in the Standby Mode by applying a High to the Chip Enable (E) input. When in the Standby Mode the outputs are in a high impedance state, independant of the Output Enable (G) input.
Output Disable Mode. When the Output Enable (G) is High the outputs are in a high impedance state. Electronic Signature Mode. This mode allows the read out of two binary codes from the device which identify the manufacturer and device type. This mode is intended for use by programming equipment to automatically select the correct erase and programming algorithms. The Electronic Signature Mode is active when a high voltage (11.5V to 13V) is applied to address line A9 with E and G Low. With A0 Low the output data is the manufacturer code, when A0 is High the output is the device type code. All other address lines should be maintained Low while reading the codes. The electronic signature may also be accessed in Read/Write modes. READ/WRITE MODES, 11.4V VPP 12.6V When VPP is High both read and write operations may be performed. These are defined by the contents of an internal command register. Commands may be written to this register to set-up and execute, Erase, Erase Verify, Program, Program Verify and Reset modes. Each of these modes needs 2 cycles. Eah mode starts with a write operation to set-up the command, this is followed by either read or write operations. The device expects the first cycle to be a write operation and does not corrupt data at any location in the memory. Read mode is set-up with one cycle only and may be followed by any number of read operations to output data. Electronic Signature Read mode is set-up with one cycle and followed by a read cycle to output the manufacturer or device codes.
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M28F101
Table 3. Operations
VPP
(1)
Operation Read
E VIL VIL VIH VIL VIL VIL VIL VIH
G VIL VIH X VIL VIL VIH VIH X
W VIH VIH X VIH VIH VIL Pulse VIH X
A9 A9 X X VID A9 A9 X X
DQ0 - DQ7 Data Output Hi-Z Hi-Z Codes Data Output Data Input Hi-Z Hi-Z
Read Only
VPPL
Output Disable Standby Electronic Signature Read
Read/Write
(2)
VPPH
Write Output Disable Standby
Notes: 1. X = VIL or VIH. 2. Refer also to the Command table.
Table 4. Electronic Signature
Identifier Manufacturer's Code Device Code A0 VIL VIH DQ7 0 0 DQ6 0 0 DQ5 1 0 DQ4 0 0 DQ3 0 0 DQ2 0 1 DQ1 0 1 DQ0 0 1 Hex Data 20h 07h
Table 5. Commands (1)
Command Read Electronic Signature (2) Setup Erase/ Erase Erase Verify Setup Program/ Program Program Verify Reset 2 2 Write Write X X C0h FFh 2 2 Write Write A0-A16 X A0h 40h Write Read Write A0-A16 X X Data Input Data Output FFh Cycles Operation 1 2 Write Write Write 1st Cycle A0-A16 X X X DQ0-DQ7 00h 90h 20h Write Read X X 20h Data Output Read Read 2 00000h 00001h 20h 07h Operation 2nd Cycle A0-A16 DQ0-DQ7
Notes: 1. X = VIL or VIH. 2. Refer also to the Electronic Signature table.
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M28F101
Table 6. AC Measurement Conditions
SRAM Interface Levels Input Rise and Fall Times Input Pulse Voltages Input and Output Timing Ref. Voltages 10ns 0 to 3V 1.5V EPROM Interface Levels 10ns 0.45V to 2.4V 0.8V and 2V
Figure 3. AC Testing Input Output Waveform
Figure 4. AC Testing Load Circuit
1.3V
SRAM Interface 3V 1.5V 0V DEVICE UNDER TEST 2.0V 0.8V
AI01275
1N914
3.3k
EPROM Interface 2.4V
OUT CL = 30pF or 100pF
0.45V
CL = 30pF for SRAM Interface CL = 100pF for EPROM Interface CL includes JIG capacitance
AI01276
Table 7. Capacitance (1) (TA = 25 C, f = 1 MHz )
Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Condition VIN = 0V VOUT = 0V Min Max 6 12 Unit pF pF
Note: 1. Sampled only, not 100% test.ed
READ/WRITE MODES (cont'd) A write to the command register is made by bringing W Low while E is Low. The falling edge of W latches Addresses, while the rising edge latches Data, which are used for those commands that require address inputs, command input or provide data output. The supply voltage VCC and the program voltage VPP can be applied in any order. When the device is powered up or when VPP is 6.5V the contents of the command register defaults to 00h, thus automatically setting-up Read operations. In addition a specific command may be used to set the command register to 00h for reading the memory.
The system designer may chose to provide a constant high VPP and use the register commands for all operations, or to switch the VPP from low to high only when needing to erase or program the memory. All command register access is inhibited when VCC falls below the Erase/Write Lockout Voltage (VLKO) of 2.5V. If the device is deselected during Erasure, Programming or Verification it will draw active supply currents until the operations are terminated. The device is protected against stress caused by long erase or program times. If the end of Erase or Programming operations are not terminated by a Verify cycle within a maximum time permitted, an internal stop timer automatically stops the operation. The device remains in an inactive state, ready to start a Verify or Reset Mode operation.
5/23
M28F101
Table 8. DC Characteristics (TA = 0 to 70 C, -40 to 85 C or -40 to 125 C; VCC = 5V 10%)
Symbol ILI ILO ICC ICC1 ICC2 ICC3 ICC4 ICC5
(1) (1) (1) (1)
Parameter Input Leakage Current Output Leakage Current Supply Current (Read) Supply Current (Standby) TTL Supply Current (Standby) CMOS Supply Current (Programming) Supply Current (Program Verify) Supply Current (Erase) Supply Current (Erase Verify) Program Leakage Current Program Current (Read or Standby) Program Current (Programming) Program Current (Program Verify) Program Current (Erase) Program Current (Erase Verify) Input Low Voltage Input High Voltage TTL Input High Voltage CMOS
Test Condition 0V VIN VCC 0V VOUT VCC E = VIL, f = 6MHz E = VIH E = VCC 0.2V During Programming During Verify During Erasure During Erase Verify VPP VCC VPP > VCC VPP VCC VPP = VPPH, During Programming VPP = VPPH, During Verify VPP = VPPH, During Erase VPP = VPPH, During Erase Verify
Min
Max 1 10 30 1 50 10 15 15 15 10 120 10 30 5 30 5
Unit A A mA mA A mA mA mA mA A A A mA mA mA mA V V V V V V V V
ILPP IPP IPP1(1) IPP2
(1)
IPP3(1) IPP4
(1)
VIL VIH
-0.5 2 0.7 VCC IOL = 5.8mA (grade 1) IOL = 2.1mA (grade 6)
0.8 VCC + 0.5 VCC + 0.5 0.45 0.45
VOL
Output Low Voltage
VOH
Output High Voltage CMOS Output High Voltage TTL
IOH = -100A IOH = -2.5mA IOH = -2.5mA
4.1 0.85 VCC 2.4 0 11.4 11.5 6.5 12.6 13 200 2.5
VPPL VPPH VID IID
(1)
Program Voltage (Read Operations) Program Voltage (Read/Write Operations) A9 Voltage (Electronic Signature) A9 Current (Electronic Signature) Supply Voltage, Erase/Program Lock-out A9 = VID
V V V A V
VLKO
Note: 1. Not 100% tested. Characterisation Data available.
6/23
M28F101
Table 9A. Read Only Mode AC Characteristics (TA = 0 to 70 C, -40 to 85 C or -40 to 125 C; 0V VPP 6.5V)
M28F101 -70 Symbol Alt Parameter Test Condition VCC=5V5% SRAM Interface Min tWHGL tAVAV tAVQV tELQX (1) tELQV tGLQX (1) tGLQV tEHQZ (1) tGHQZ
(1)
-90
-100 Unit
VCC=5V10% VCC=5V10% EPROM Interface Min 6 90 Max EPROM Interface Min 6 100 90 0 0 90 0 0 40 0 0 0 45 30 0 0 0 45 45 30 100 100 Max
Max
Write Enable High to Output Enable Low tRC tACC tLZ tCE tOLZ tOE Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z tDF tOH Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL
6 70 70 0 70 0 40 0 0 0 30 30
s ns ns ns ns ns ns ns ns ns
tAXQX
Note: 1. Sampled only, not 100% tested
Read Mode. The Read Mode is the default at power up or may be set-up by writing 00h to the command register. Subsequent read operations output data from the memory. The memory remains in the Read Mode until a new command is written to the command register. Electronic Signature Mode. In order to select the correct erase and programming algorithms for onboard programming, the manufacturer and device
codes may be read directly. It is not neccessary to apply a high voltage to A9 when using the command register. The Electronic Signature Mode is set-up by writing 90h to the command register. The following read cycles, with address inputs 00000h or 00001h, output the manufacturer or device type codes. The command is terminated by writing another valid command to the command register (for example Reset).
7/23
M28F101
Table 9B. Read Only Mode AC Characteristics ((TA = 0 to 70 C, -40 to 85 C or -40 to 125 C; 0V VPP 6.5V)
M28F101 -120 Symbol Alt Parameter Test Condition -150 -200 Unit
VCC=5V10% VCC=5V10% VCC=5V10% EPROM Interface Min Max EPROM Interface Min 6 150 120 0 120 0 50 0 0 0 55 30 0 0 0 0 55 55 35 0 0 0 0 150 0 60 60 40 150 0 200 Max EPROM Interface Min 6 200 200 Max
tWHGL tAVAV tAVQV tELQX (1) tELQV tGLQX (1) tGLQV tEHQZ (1) tGHQZ
(1)
Write Enable High to Output Enable Low tRC tACC tLZ tCE tOLZ tOE Read Cycle Time Address Valid to Output Valid Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z tDF tOH Output Enable High to Output Hi-Z Address Transition to Output Transition E = VIL, G = VIL E = VIL, G = VIL G = VIL G = VIL E = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL
6 120
s ns ns ns ns ns ns ns ns ns
tAXQX
Note: 1. Sampled only, not 100% tested
Erase and Erase Verify Modes. The memory is erased by first Programming all bytes to 00h, the Erase command then erases them to FFh. The Erase Verify command is then used to read the memory byte-by-byte for a content of FFh. The Erase Mode is set-up by writing 20h to the command register. The write cycle is then repeated to start the erase operation. Erasure starts on the rising edge of W during this second cycle. Erase is followed by an Erase Verify which reads an addressed byte.
Erase Verify Mode is set-up by writing A0h to the command register and at the same time supplying the address of the byte to be verified. The rising edge of W during the set-up of the first Erase Verify Mode stops the Erase operation. The following read cycle is made with an internally generated margin voltage applied; reading FFh indicates that all bits of the addressed byte are fully erased. The whole contents of the memory are verified by repeating the Erase Verify Operation, first writing the set-up code A0h with the address of the byte to be verified and then reading the byte contents in a second read cycle.
8/23
M28F101
Figure 5. Read Mode AC Waveforms
tAVAV A0-A16 tAVQV E tELQV tELQX G tGLQV tGLQX DQ0-DQ7 DATA OUT tGHQZ tEHQZ tAXQX
AI00671
Figure 6. Read Command Waveforms
VPP tVPHEL A0-A16 tAVQV E tELWL G tGHWL W tWLWH tDVWH DQ0-DQ7 COMMAND tWHDX DATA OUT tGLQV tWHGL tGHQZ tWHEH tELQV tEHQZ VALID tAXQX
READ SET-UP
READ
AI00672
9/23
M28F101
Figure 7. Electronic Signature Command Waveforms
VPP tVPHEL A0-A16 tAVQV E tELWL G tGHWL W tWLWH tDVWH DQ0-DQ7 COMMAND tWHDX DATA OUT tGLQV tWHGL tGHQZ tWHEH tELQV tEHQZ 00000h-00001h tAXQX
READ ELECTRONIC SIGNATURE SET-UP
READ MANUFACTURER OR DEVICE
AI00673
READ/WRITE MODES (cont'd) As the Erase algorithm flow chart shows, when the data read during Erase Verify is not FFh, another Erase operation is performed and verification continues from the address of the last verifiedbyte. The command is terminated by writing another valid command to the command register (for example Program or Reset). Program and Program Verify Modes. The Program Mode is set-up by writing 40h to the command register. This is followed by a second write cycle which latches the address and data of the byte to be programmed. The rising edge of W during this secind cycle starts the programming operation. Programming is followed by a Program Verify of the data written.
ProgramVerify Mode is set-up by writing C0h to the command register. The rising edge of W during the set-up of the Program Verify Mode stops the Programming operation. The following read cycle, of the address already latched during programming, is made with an internally generated margin voltage applied,reading valid data indicates that all bits have been programmed. Reset Mode. This command is used to safely abort Erase or Program Modes. The Reset Mode is set-up and performed by writing FFh two times to the command register. The command should be followed by writing a valid command to the the command register (for example Read).
10/23
M28F101
Table 10A. Read/Write Mode AC Characteristics, W and E Controlled (TA = 0 to 70 C, -40 to 85 C or -40 to 125 C)
M28F101 -70 Symbol Alt Parameter VCC=5V5% SRAM Interface Min tVPHEL tVPHWL tWHWH3 tAVWL tAVEL tWLAX tELAX tELWL tWLEL tGHWL tGHEL tDVWH tDVEH tWLWH tELEH tWHDX tEHDX tWHWH1 tEHEH1 tWHWH2 tWHEH tEHWH tWHWL tEHEL tWHGL tEHGL tAVQV tELQX tGLQX tEHQZ tGHQZ
(1)
-90 VCC=5V10% EPROM Interface Min 1 1 90 0 0 40 60 15 0 0 0 40 35 40 45 10 10 9.5 9.5 9.5 0 0 20 20 6 6 70 90 0 70 90 0 40 30 30 40 40 30 0 0 0 0 Max
-100 VCC=5V10% EPROM Interface Min 1 1 100 0 0 40 60 15 0 0 0 40 40 40 45 10 10 9.5 9.5 9.5 0 0 20 20 6 6 100 100 45 40 30 Max s s ns ns ns ns ns ns ns s s ns ns ns ns ns ns s s ms ns ns ns ns s s ns ns ns ns ns ns ns ns Unit
Max
VPP High to Chip Enable Low VPP High to Write Enable Low tWC tAS tAH tCS Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Chip Enable Low to Write Enable Low Write Enable Low to Chip Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low tDS Input Valid to Write Enable High Input Valid to Chip Enable High tWP Write Enable Low to Write Enable High (Write Pulse) Chip Enable Low to Chip Enable High (Write Pulse) tDH Write Enable High to Input Transition Chip Enable High to Input Transition Duration of Program Operation Duration of Program Operation Duration of Erase Operation tCH tWPH Write Enable High to Chip Enable High Chip Enable High to Write Enable High Write Enable High to Write Enable Low Chip Enable High to Chip Enable Low Write Enable High to Output Enable Low Chip Enable High to Output Enable Low tACC tLZ tCE tOLZ tOE tDF tOH Addess Valid to data Output Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
1 1 70 0 0 40 50 10 0 0 0 30 30 35 35 10 10 9.5 9.5 9.5 0 0 20 20 6 6 0 0
tELQV
(1)
tGLQV
(1) (1)
tAXQX
0
Note: 1. Sampled only, not 100% tested.
11/23
M28F101
Table 10B. Read/Write Mode AC Characteristics, W and E Controlled (TA = 0 to 70 C, -40 to 85 C or -40 to 125 C)
M28F101 -120 Symbol Alt Parameter VCC=5V10% EPROM Interface Min tVPHEL tVPHWL tWHWH3 tAVWL tAVEL tWLAX tELAX tELWL tWLEL tGHWL tGHEL tDVWH tDVEH tWLWH tELEH tWHDX tEHDX tWHWH1 tEHEH1 tWHWH2 tWHEH tEHWH tWHWL tEHEL tWHGL tEHGL tAVQV tELQX tGLQX tEHQZ tGHQZ
(1)
-150 VCC=5V10% EPROM Interface Min 1 1 150 0 0 60 80 20 0 0 0 50 50 60 70 10 10 9.5 9.5 9.5 0 0 20 20 6 6 120 150 0 120 150 0 50 50 30 55 55 35 0 0 0 0 Max
-200 VCC=5V10% EPROM Interface Min 1 1 200 0 0 75 80 20 0 0 0 50 50 60 70 10 10 9.5 9.5 9.5 0 0 20 20 6 6 200 200 60 60 40 Max s s ns ns ns ns ns ns ns s s ns ns ns ns ns ns s s ms ns ns ns ns s s ns ns ns ns ns ns ns ns Unit
Max
VPP High to Chip Enable Low VPP High to Write Enable Low tWC tAS tAH tCS Write Cycle Time Address Valid to Write Enable Low Address Valid to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Chip Enable Low to Write Enable Low Write Enable Low to Chip Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low tDS Input Valid to Write Enable High Input Valid to Chip Enable High tWP Write Enable Low to Write Enable High (Write Pulse) Chip Enable Low to Chip Enable High (Write Pulse) tDH Write Enable High to Input Transition Chip Enable High to Input Transition Duration of Program Operation Duration of Program Operation Duration of Erase Operation tCH tWPH Write Enable High to Chip Enable High Chip Enable High to Write Enable High Write Enable High to Write Enable Low Chip Enable High to Chip Enable Low Write Enable High to Output Enable Low Chip Enable High to Output Enable Low tACC tLZ tCE tOLZ tOE tDF tOH Addess Valid to data Output Chip Enable Low to Output Transition Chip Enable Low to Output Valid Output Enable Low to Output Transition Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
1 1 120 0 0 60 80 20 0 0 0 50 50 60 70 10 10 9.5 9.5 9.5 0 0 20 20 6 6 0 0
tELQV
(1)
tGLQV
(1) (1)
tAXQX
0
Note: 1. Sampled only, not 100% tested.
12/23
ERASE OPERATION
VPP
tVPHEL VALID tWHWH3 tAVWL tWLAX
A0-A16
E tWHEH tELWL tWHEH tELQV tEHQZ
tELWL
G tWHWL tWHWH2 tWHGL tGHQZ
tGHWL
W tWLWH tWHDX COMMAND tDVWH COMMAND tWHDX DATA OUT tGLQV
tWLWH
tDVWH
DQ0-DQ7
COMMAND
ERASE SET-UP
Figure 8. Erase Set-up and Erase Verify Commands Waveforms, W Controlled
ERASE SET-UP (REPEAT OF 1st CYCLE)
ERASE VERIFY SET-UP
VERIFY READ
AI00674
M28F101
13/23
14/23
ERASE OPERATION VALID tWHWH3 tAVEL tELAX tEHWH tWLEL tEHWH tGLQV tEHEL tEHEH2 tEHGL tGHQZ tELEH tEHDX COMMAND tDVEH COMMAND tELQV tEHDX DATA OUT tEHQZ ERASE SET-UP (REPEAT OF 1st CYCLE) ERASE VERIFY SET-UP VERIFY READ
AI01313
M28F101
VPP
tVPHWL
A0-A16
W
tWLEL
G
tGHEL
E
tELEH
tDVEH
DQ0-DQ7
COMMAND
Figure 9. Erase Set-up and Erase Verify Commands Waveforms, E Controlled
ERASE SET-UP
PROGRAM OPERATION
VPP
tVPHEL VALID tAVWL tWHWH3 tWLAX
A0-A16
E tWHEH tWHEH tELQV tEHQZ
tELWL
tWHEH
G tELWL tWHWL tWHWH1 tELWL tWHGL tGHQZ
tGHWL
W tWLWH tWHDX tDVWH DATA IN tWHDX tDVWH COMMAND tWLWH tWHDX DATA OUT tGLQV
tWLWH
tDVWH
DQ0-DQ7
COMMAND
PROGRAM SET-UP ADDRESS AND DATA LATCH
Figure 10. Program Set-up and Program Verify Commands Waveforms, W Controlled
PROGRAM VERIFY SET-UP
VERIFY READ
AI00675
M28F101
15/23
16/23
PROGRAM OPERATION VALID tAVEL tELAX tWHWH3 tEHWH tEHWH tGLQV tWLEL tEHEL tEHEH1 tWLEL tEHGL tGHQZ tELEH tEHDX tDVEH DATA IN tEHDX tDVEH COMMAND tELEH tELQV tEHDX DATA OUT tEHQZ ADDRESS AND DATA LATCH PROGRAM VERIFY SET-UP VERIFY READ
AI00676
M28F101
VPP
tVPHEL
A0-A16
W
tWLEL
tEHWH
G
tGHEL
E
tELEH
tDVEH
DQ0-DQ7
COMMAND
Figure 11. Program Set-up and Program Verify Commands Waveforms, E Controlled
PROGRAM SET-UP
M28F101
Figure 12. Erasing Flowchart
VPP = 12V VPP = 12V PROGRAM ALL BYTES TO 00h n=0 n=0, Addr=00000h PROGRAM SET-UP Latch Addr, Data Wait 10s NO YES ++n = 25 PROGRAM VERIFY Wait 6s READ DATA OUTPUT
Figure 13. Programming Flowchart
ERASE SET-UP Wait 10ms
NO YES ++n LIMIT
ERASE VERIFY Latch Addr. Wait 6s READ DATA OUTPUT
VPP < 6.5V FAIL
VPP < 6.5V FAIL
NO NO Data OK YES Last Addr NO Addr++
Data OK YES Last Addr NO
Addr++
YES READ COMMAND VPP < 6.5V, PASS
YES READ COMMAND
AI00677
VPP < 6.5V, PASS
AI00678
Limit: 1000 at grade 1; 6000 at grades 3 & 6.
PRESTO F ERASE ALGORITHM The PRESTO F Erase Algorithm guarantees that the device will be erased in a reliable way. The algorithm first programms all bytes to 00h in order to ensure uniform erasure. The programming follows the PRESTO F Programming Algorithm. Erase is set-up by writing 20h to the command register, the erasure is started by repeating this write cycle. Erase Verify is set-up by writing A0h to the command register together with the address of the byte to be verified. The subsequent read cycle reads the data which is compared to FFh. Erase Verify begins at address 0000h and continues to the last address or until the comparison of the data to 0FFh fails. If this occurs, the address of the last byte checked is stored and a new Erase operation performed. Erase Verify then continues from the address of the stored location.
PRESTO F PROGRAM ALGORITHM The PRESTO F Programming Algorithm applies a series of 10s programming pulses to a byte until a correct verify occurs. Up to 25 programming operations are allowed for one byte. Program is set-up by writing 40h to the command register, the programming is started after the next write cycle which also latches the address and data to be programmed. Program Verify is set-up by writing C0h to the command register, followed by a read cycle and a compare of the data read to the data expected. During Program and Program Verify operations a MARGIN MODE circuit is activated to guaranteethat the cell is programmed with a safety margin.
17/23
M28F101
ORDERING INFORMATION SCHEME
Example:
M28F101
-70
X
N
1
TR
Operating Voltage F 5V R
Option Reverse Pinout TR Tape & Reel Packing
Speed -70 -90 -100 -120 -150 -200 70ns 90ns 100ns 120ns 150ns 200ns
Power Supplies blank X VCC 10% VCC 5% P K N
Package PDIP32 PLCC32 TSOP32 8 x 20mm 1 3 6
Temp. Range 0 to 70 C -40 to 125 C -40 to 85 C
Devices are shipped from the factory with the memory content erased (to FFh). For a list of available options (Speed, Package, etc...) or for further information on any aspect of this device, please contact the SGS-THOMSON Sales Office nearest to you.
18/23
M28F101
PDIP32 - 32 pin Plastic DIP, 600 mils width
Symb Typ A A1 A2 B B1 C D E E1 e1 eA L S N
PDIP32
mm Min Max 4.83 0.38 - - 0.41 1.14 0.20 41.78 15.24 13.46 2.54 15.24 - - 3.18 1.78 0 32 - - 0.51 1.40 0.30 42.04 15.88 13.97 - - 3.43 2.03 15 0.100 0.600 - Typ
inches Min Max 0.190 0.015 - 0.016 0.045 0.008 1.645 0.600 0.530 - - 0.125 0.070 0 32 - - 0.020 0.055 0.012 1.655 0.625 0.550 - - 0.135 0.080 15
A2 A1 B1 D S
N
A L eA C
B
e1
E1
1
E
PDIP
Drawing is not to scale.
19/23
M28F101
PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symb Typ A A1 B B1 D D1 D2 E E1 E2 e N Nd Ne CP
PLCC32
mm Min 2.54 1.52 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 1.27 - 32 7 9 0.10 Max 3.56 2.41 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.050 Typ
inches Min 0.100 0.060 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - 32 7 9 0.004 Max 0.140 0.095 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 -
D D1
1N
A1
B1
Ne
E1 E
D2/E2 B
e
Nd
A CP
PLCC
Drawing is not to scale.
20/23
M28F101
TSOP32 Normal Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
Symb Typ A A1 A2 B C D D1 E e L N CP
TSOP32
mm Min 1.04 0.05 0.95 0.15 0.10 19.90 18.24 7.90 0.50 - 0.30 0 32 0.10 Max 1.24 0.20 1.06 0.27 0.21 20.12 18.49 8.10 - 0.70 5 0.020 Typ
inches Min 0.041 0.002 0.037 0.006 0.004 0.783 0.718 0.311 - 0.012 0 32 0.004 Max 0.049 0.008 0.042 0.011 0.008 0.792 0.728 0.319 - 0.028 5
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
Drawing is not to scale.
A1
L
21/23
M28F101
TSOP32 Reverse Pinout - 32 lead Plastic Thin Small Outline, 8 x 20mm
Symb Typ A A1 A2 B C D D1 E e L N CP
TSOP32
mm Min 1.04 0.05 0.95 0.15 0.10 19.90 18.24 7.90 0.50 - 0.30 0 32 0.10 Max 1.24 0.20 1.06 0.27 0.21 20.12 18.49 8.10 - 0.70 5 0.020 Typ
inches Min 0.041 0.002 0.037 0.006 0.004 0.783 0.718 0.311 - 0.012 0 32 0.004 Max 0.049 0.008 0.042 0.011 0.008 0.792 0.728 0.319 - 0.028 5
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-b
Drawing is not to scale.
A1
L
22/23
M28F101
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1997 SGS-THOMSON Microelectronics - All Rights Reserved
SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
23/23

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